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Integrated Circuit Systems, Inc.
LOW SKEW 1, 2 CLOCK GENERATOR
FEATURES
20 LVCMOS outputs, 7 typical output impedance Output frequency up to 250 MHz 150ps bank skew, 200ps output, 250ps multiple frequency skew, 650ps part-to-part skew Translates any differential input signal (PECL, HSTL, LVDS) to LVCMOS levels without external bias networks Translates any single-ended input signal to LVCMOS levels with a resistor bias on nCLK input Translates any single-ended input signal to inverted LVCMOS levels with a resistor bias on CLK input LVCMOS / LVTTL control inputs Bank enable logic allows unused banks to be disabled in reduced fanout applications 3.3V or mixed 3.3V input, 2.5V output operating supply modes 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch 0C to 70C ambient operating temperature Other divide values available on request
ICS8702
The ICS8702 is a very low skew, /1, /2 Clock Generator and a member of the HiPerClockS HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8702 is designed to translate any differential signal levels to LVCMOS levels. True or inverting, single-ended to LVCMOS translation can be achieved with a resistor bias on the nCLK or CLK inputs, respectively. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
GENERAL DESCRIPTION
,&6
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The bank enable inputs, BANK_EN0:1, supports enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the enabling and disabling of all outputs simultaneously. The ICS8702 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK nCLK DIV_SELA
1 0 /1 /2 1 0
PIN ASSIGNMENT
GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND
QAO - QA4 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4
QB0 - QB4
DIV_SELB
1 0
QC0 - QC4
DIV_SELC
1 0
QD0 - QD4
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8702
QB1 VDDO QB0 QA4 VDD0 QA3 GND QA2 GND QA1 VDDO QA0
DIV_SELA DIV_SELB CLK nCLK VDDI BANK_EN0 GND BANK_EN1 VDDI nMR/OE DIV_SELC DIV_SELD
DIV_SELD nMR/OE BANK_EN0 BANK_EN1
Bank Enable Logic
48-Lead LQFP Y Package Top View
8702
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 28, 30, 37, 39, 46, 48 16, 20 18 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 21 13 14 23 24 17, 19 15 Name VDDO GND VDDI GND QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK nCLK DIV_SELD DIV_SELC DIV_SELB DIV_SELA BANK_EN1, BANK_EN0 nMR/OE Pow er Pow er Pow er Pow er Output Output Output Output Input Input Input Input Input Input Input Input Pulldow n Pullup Pullup Pullup Pullup Pullup Pullup Pullup Ty pe Description
LOW SKEW 1, 2 CLOCK GENERATOR
ICS8702
Output pow er supply. Connect to 3.3V or 2.5V. Output pow er supply. Connect to ground. Input pow er supply. Connect to 3.3V. Input pow er supply. Connect to ground. Bank A outputs. 7 typical output impedance. Bank B outputs. 7 typical output impedance. Bank C outputs. 7 typical output impedance. Bank D outputs. 7 typical output impedance. Non-inverting differential clock input. Accepts any differential levels. Inverting differential clock input. Accepts any differential levels. Controls frequency division for bank D outputs. LVCMOS interface levels. Controls frequency division for bank C outputs. LVCMOS interface levels. Controls frequency division for bank B outputs. LVCMOS interface levels. Controls frequency division for bank A outputs. LVCMOS interface levels. Enables and disables outputs by banks. LVCMOS interface levels. Asynchronous master reset. Resets clock dividers. Enables and disables all outputs. LVCMOS interface levels.
TABLE 2. PIN CHARACTERISTICS
Sy mbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldow n Resistor Pow er Dissipation Capacitance (per output) Output Impedance VDDI, VDDO = 3.465V VDDI = 3.465V, VDDO = 2.625V 7 51 51 Test Conditions Minimum Ty pical Maximum Units pF K K pF pF
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
Inputs nMR/OE 0 1 1 1 1 1 1 1 1 BANK_EN1 X 0 1 0 1 0 1 0 1 BANK_EN0 X 0 0 1 1 0 0 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 QA0 - QA4 Hi Z Active Active Active Active Active Active Active Active QB0 - QB4 Hi Z Hi Z Active Active Active Hi Z Active Active Active Hi Z Hi Z Hi Z Active Active Hi Z Hi Z Active Active Outputs QC0 - QC4 QD0 - QD4 Hi Z Hi Z Hi Z Hi Z Active Hi Z Hi Z Hi Z Active Qx frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
TABLE 3B. CLOCK INPUTS FUNCTION TABLE
Inputs nMR/OE 1 1 1 1 1 CLK 0 1 0 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 Outputs Qx0 thru Qx4 LOW HIGH LOW HIGH HIGH
LOW SKEW 1, 2 CLOCK GENERATOR
Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Polarity Non Inverting Non Inverting Non Inverting Non Inverting Inverting
ICS8702
1 Biased; NOTE 1 1 LOW Single Ended to Single Ended Inverting NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets the sw itch point for the single ended input. For LVCMOS input levels the recommended input bias netw ork is a resistor to VDDI, a resistor of equal value to ground and a 0.1F capacitor from the input to ground. The resulting sw itch point is approximately VDD/2 300mV.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 0C to 70C -65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8702
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
TABLE 4A. DC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V5%, TA=0C TO 70C
Sy mbol VDDI VDDO VIH VIL VPP VCM R Parameter Input Pow er Supply Voltage Output Pow er Supply Voltage Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common M ode Input Voltage; NOTE 1 Input High Current Input Low Current All except CLK, nCLK All except CLK, nCLK; CLK, nCLK CLK, nCLK All except CLK CLK All except CLK CLK LVPECL Levels DCM , HSTL, LVDS, SSTL Levels VDDI = VIN = 3.465V VDDI = VIN = 3.465V VDDI = 3.465, VIN = 0V VDDI = 3.465, VIN = 0 -150 -5 VDDI = 3.465V VDDI = 3.135V Test Conditions
LOW SKEW 1, 2 CLOCK GENERATOR
Minimum 3.135 3.135 2 -0.3 0.15 1.8 0.31 Ty pical 3.3 3.3 Maximum 3.465 3.465 3.8 0.8 1.3 2.4 1.3 5 150 Units V V V V V V V A A A A
ICS8702
IIH IIL IDD
VDDI = VIH = 3.465V 70 mA VIL = 0V VDDI = VDDO = 3.135V 2.6 V VOH Output High Voltage IOH = -36mA VDDI = VDDO = 3.135V VOL Output Low Voltage 0.5 V IOL = 36mA NOTE 1: Common mode input voltage for LVPECL is defined as the minimum VIH. The LVPECL values noted in Table 4A are for VCCI = 3.3V. VCM R for LVPECL w ill vary 1:1 w ith VCCI. Common mode input voltage for DCM , HSTL, LVDS and SSTL is defined as the crossover voltage. See Figure 1. Quiescent Pow er Supply Current
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V5%, TA=0C TO 70C
Sy mbol fMAX tpLH tpHL tsk(b) tsk(o) tsk() tsk(pp) tR tF tPW tEN tDIS NOTE 1: NOTE 2: NOTE 3: NOTE 4: NOTE 5: NOTE 6: Parameter Maximum Input Frequency Propagation Delay, Low -to-High Propagation Delay, High-to-Low Bank Skew ; NOTE 2 Output Skew ; NOTE 3 Multiple Frequency Skew ; NOTE 4 Part to Part Skew ; NOTE 5 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width Output Enable Time; NOTE 6 0MHZ < f 200MHz 0MHZ < f 200MHz Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 30% to 70% 30% to 70% 0MHZ < f < 200MHz f = 200MHz f = 10MHz 280 280 tCY CLE/2 - 0.5 2 tCY CLE/2 2.5 2.2 2.2 Test Conditions Minimum Ty pical Maximum 250 3.5 3.5 150 200 250 650 850 850 tCY CLE/2 + 0.5 3 6 Units MHz ns ns ps ps ps ps ps ps ns ns ns
Output Disable Time; NOTE 6 f = 10MHz 6 ns All parameters measured at fIN = 200MHz and VPP = 300mV unless noted otherw ise. All outputs terminated w ith 50 to VDDO/2. Defined as skew w ithin a bank of outputs at the same supply voltages and w ith equal load conditions. Defined as skew across banks of outputs at the same supply voltages and w ith equal load conditions. Defined as skew across banks of outputs operating at different frequency w ith the same supply voltages and equal load conditions. Defined as the skew at different outputs on different devices operating at the same supply voltages and w ith equal load conditions. These parameters are guaranteed by characterization. Not tested in production.
8702
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
LOW SKEW 1, 2 CLOCK GENERATOR
Test Conditions Minimum 3.135 2.375 VDDI = 3.465V VDDI = 3.135V 2 -0.3 0.15 LVPECL Levels DCM, HSTL, LVDS, SSTL Levels VDDI = VIN = 3.465V VDDI = VIN = 3.465V VDDI = 3.465V, VIN = 0V VDDI = 3.465V, VIN = 0V -150 -5 1.8 0.31 Ty pical 3.3 2.5 Maximum 3.465 2.625 3.8 0.8 1.3 2.4 1.3 5 150 A A A A Units V V V V
ICS8702
TABLE 4B. DC ELECTRICAL CHARACTERISTICS, VDDI=3.3V5%, VDDO=2.5V5%, TA=0C TO 70C
Sy mbol VDDI VDDO VIH VIL VPP VCMR IIH IIL IDD Parameter Input Pow er Supply Voltage Output Pow er Supply Voltage Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1 Input High Current Input Low Current All except CLK, nCLK All except CLK, nCLK CLK, nCLK CLK, nCLK All except CLK CLK All except CLK CLK
VDDI = VIH = 3.465V 70 mA VIL = 0V VDDI = 3.135V, VDDO = 2.375V 1.9 V VOH Output High Voltage IOH = -27mA VDDI = 3.135V, VDDO = 2.375V 0.5 V VOL Output Low Voltage IOL = 27mA NOTE 1: Common mode input voltage for LVPECL is defined as the minimum VIH. The LVPECL values noted in Table 4B are for VCCI = 3.3V. VCMR for LVPECL w ill vary 1:1 w ith VCCI. Common mode input voltage for DCM, HSTL, LVDS and SSTL is defined as the crossover voltage. See Figure 1. Quiescent Pow er Supply Current
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VDDI=3.3V5%, VDDO=2.5V5%, TA=0C TO 70C
Sy mbol fMAX tpLH tpHL tsk(b) tsk(o) tsk() tsk(pp) tR tF tPW tEN tDIS NOTE 1: NOTE 2: NOTE 3: NOTE 4: NOTE 5: NOTE 6: Parameter Maximum Input Frequency Propagation Delay, Low -to-High Propagation Delay, High-to-Low Bank Skew ; NOTE 2 Output Skew ; NOTE 3 Multiple Frequency Skew ; NOTE 4 Part to Part Skew ; NOTE 5 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width Output Enable Time; NOTE 6 0MHZ < f 200MHz 0MHZ < f 200MHz Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 30% to 70% 30% to 70% 0MHZ < f < 200MHz f = 200MHz f = 10MHz 280 280 tCY CLE/2 - 0.5 2 tCY CLE/2 2.5 2.3 2.3 Test Conditions Minimum Ty pical Maximum 250 3.6 3.6 150 200 250 700 850 850 tCY CLE/2 + 0.5 3 6 Units MHz ns ns ps ps ps ps ps ps ns ns ns
Output Disable Time; NOTE 6 f = 10MHz 6 ns All parameters measured at fIN = 200MHz and VPP = 300mV unless noted otherw ise. All outputs terminated w ith 50 to VDDO/2. Defined as skew w ithin a bank of outputs at the same supply voltages and w ith equal load conditions. Defined as skew across banks of outputs at the same supply voltages and w ith equal load conditions. Defined as skew across banks of outputs operating at different frequency w ith the same supply voltages and equal load conditions. Defined as the skew at different outputs on different devices operating at the same supply voltages and w ith equal load conditions. These parameters are guaranteed by characterization. Not tested in production.
8702
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
FIGURE 1A, 1B - TIMING DIAGRAMS
LOW SKEW 1, 2 CLOCK GENERATOR
ICS8702
CLK
nCLK
Qx, /1
Qx, /2
FIGURE 1A - ACTIVE, /1, /2
nMR/OE
CLK
n CLK
Qx, /1
Qx, /2
High Impedance
Active
FIGURE 1B - RESET TO ACTIVE, /1, /2
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
FIGURE 2A, 2B, 2C - INPUT CLOCK WAVEFORMS
VDDI
LOW SKEW 1, 2 CLOCK GENERATOR
ICS8702
CLK
VPP nCLK
CROSS POINTS VCMR
GND
FIGURE 2A - DCM, HSTL, LVDS, SSTL DIFFERENTIAL INPUT LEVELS
VDDI
CLK
VPP nCLK
CROSS POINTS
VCMR
GND
FIGURE 2B - LVPECL DIFFERENTIAL INPUT LEVEL
VDDI CLK or nCLK GND
FIGURE 2C- LVCMOS AND LVTTL SINGLE ENDED INPUT LEVEL
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
FIGURE 3A, 3B - TIMING WAVEFORMS
CLK
LOW SKEW 1, 2 CLOCK GENERATOR
ICS8702
Vpp
nCLK tPHL Q tPLH
VDDO/2
FIGURE 3A - PROPAGATION DELAYS
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
nMR/OE, BANK_ENx
3.3V
BANK_ENx
0V tPHZ tPZH VOH - 300mV
Q
VOH
VDDO/2 tPLZ VDDO/2 VOL + 300mV tPZL
Q
VOL
FIGURE 3B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8702
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
FIGURE 4A, 4B- SKEW DEFINITIONS & WAVEFORMS
LOW SKEW 1, 2 CLOCK GENERATOR
ICS8702
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
Vpp
nCLK Qx0

VDDO/2
VDDO/2

tsk(b)
tsk(b)
Qx4
VDDO/2
VDDO/2
FIGURE 4A - BANK SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
Vpp
nCLK QA0 - QA4 VDDO/2 VDDO/2
tsk(o) QB0 - QB4 QC0 - QC4 QD0 - QD4
tsk(o)
VDDO/2
VDDO/2
FIGURE 4B - OUTPUT SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
FIGURE 4C, 4D- SKEW DEFINITIONS & WAVEFORMS
LOW SKEW 1, 2 CLOCK GENERATOR
ICS8702
Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
Vpp
nCLK QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 in /1 tsk(w) tsk(w)
VDDO/2
VDDO/2
VDDO/2 QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 in /2
VDDO/2
FIGURE 4C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
Vpp
nCLK PART 1 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4
VDDO/2
VDDO/2
tsk(p) PART 2 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4
tsk(p)
VDDO/2
VDDO/2
FIGURE 4B - OUTPUT SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX
NOTE 4 D NOTE 5, 7 D1 D/2 NOTE 3 -DD1/2
LOW SKEW 1, 2 CLOCK GENERATOR
e /2
ICS8702
-A, B, OR -D-
b NOTE 3 -ANOTE 3 -BE1 e N O T E 5, 7 N/4 T IPS 0.20 C A-B D E/2 E1/2 E N O T E 4 -A, B, OR -D-
4X
SEE DETAIL "A"
8 PLACES 11 / 13
A
-H- NOT E 2 / / 0.10 C ccc -CSEE DETAIL "B"
NOTES: 1. ALL DIMENSIONS AND TOLERANCING CONFORM TO ANSI Y14.5-1982 2. DATUM PLANE -H- LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 3. DATUMS A-B AND -D- TO BE DETERMINED AT CENTERLINE BETWEEN LEADS WHERE LEADS EXIT PLASTIC AT DATUM PLANE -H- . 4. TO BE DETERMINED AT SEATING PLACE -C- . 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. 6. "N" IS THE TOTAL NUMBER OF TERMINALS. 7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM PLANE -H-. 8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM DIMENSIONS AND TOP OF PACKAGE WILL NOT OVERHANG BOTTOM OF PACKAGE. 9. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 10. CONTROLLING DIMENSION: MILLIMETER. 11. THIS OUTLINE CONFORMS TO JEDEC PUBLIBCATION 95 REGISTRATION MS-026, VARIATION BBC. 12. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE.
NOTE 9 b
ddd M C A-B S D S WIT H LEAD FINISH
0.09 / 0.20
0.09 / 0.16
S Y M B O L A
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBC MIN. NOM. MAX. 1.60 0.05 1.35 1.40 9.00 BSC. 7.00 BSC. 9.00 BSC. 7.00 BSC. 0.45 0.60 48 0.5 BSC. 0.17 0.17 0.22 0.20 0.27 0.23 0.08 0.08 0.75 0.15 1.45
N O T E
b1 BASE METAL
A1 A2 D D1
12
4 7, 8 4 7, 8
0 MIN. - 0.05 S A2 DATUM PLANE -H0.08/0.20 R. 0.25 GAUGE PLANE
E E1 L N e
A1
0.08 R. MIN. 0.20 MIN. 1.00 REF.
b 0 - 7 L b1 ccc ddd
9
8702
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REV. A - AUGUST 7, 2000
Integrated Circuit Systems, Inc.
ORDERING INFORMATION
Part/Order Number ICS8702BY ICS8702BY T Marking ICS8702BY ICS8702BY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel
LOW SKEW 1, 2 CLOCK GENERATOR
Count 250 per tray 2000 Temperature 0C to 70C 0C to 70C
ICS8702
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8702
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